ECC with BCH Algorithm (IPC-BL119A-ZM)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V


Supported Device Family: 

Solution Type: 


The IntelliProp IPC-BL119A-ZM is a highly configurable IP core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels. The ECC core uses the industry standard BCH class of error correcting codes. Applications for the iPC-BL119A-ZM include: Data Storage devices (SATA, SAS, FLASH); Satellite communications / telemetry; Radiowave signal recording; Wireless communications; High-speed modems such as ADSL, xDSL, etc.; Power line standards.


  • High bandwidth, low latency parallel encode and decode paths
  • Configurable number of encode/decode blocks
  • Configurable code word length (K), up to 1024 bytes
  • Configurable 32, 64, 128, or 256 “FIFO” data interface
  • User selectable error correction values (T)

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at to discuss specific needs for your project.

IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Simulation Script, Sample Vectors
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportn/a
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone V,
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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