IntelliProp NVMe Host Accelerator IP Core (IPC-NV164-HI)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Stratix Series: Stratix V

Overview

IntelliProp’s IPC-NV164-HI NVMe Host Accelerator IP Core provides a simplified, high-bandwidth interface to industry standard NVMe storage devices. The IntelliProp NVMe Host Accelerator Core provides a small footprint processor register interface or RTL state-machine register interface for data movement between a user-defined data buffer and an NVMe target. Additionally, the NVMe Host Accelerator IP Core requires minimal knowledge of the PCIe and NVMe specification. The IP Core handles initialization of the PCIe Root Complex, building command submissions, parsing command completions. The protocol interface is compliant to the NVM Express 1.3 specification and is fully verified using a coverage driven methodology in pseudo random simulation. Applications for the IPC-NV164A-HI include: Protocol-X to NVMe Bridge; NVMe to NVMe Bridge Systems; NVMe Fabric Accelerators; NVMe RAID Applications; Embedded applications requiring non-volatile storage.

Features

    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

    Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Encrypted Verilog; simulation model, reference design, synthesis & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Stratix V, Cyclone V, Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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