IntelliProp NVMe Target IP Core (IPC-NV163A-DT)

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V

Stratix Series: Stratix V

Overview

The IntelliProp IPC-NV163A-DT is an industry standard NVMe Target IP core that allows customers to build high speed NVMe (PCIe) storage devices. The IPC-NV163A-DT provides a hardware accelerated queue management interface for NVMe commands and completions as well as provides the NVMe controller register interface for host communication and controller management. The NVMe Target Core is available for integration into Intel FPGA designs to provide an industry compliant NVMe interface at PCIe Gen3, Gen2 or Gen1 speeds. Target applications include: • NVMe SSD Controllers • NVMe fabric devices • NVMe Bridge Systems

Features

    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

    Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    RTL Encrypted code; simulation script; synthesis or place & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportlinux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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