IntelliProp NVMe Target IP Core

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10

Overview

IntelliProp’s NVMe Target IP Core (IPC-NV163A-DT) is an industry standard NVMe device interface core that allows companies to build high speed PCIe based storage devices. The protocol interface is compliant to the NVMe 1.2 specification and is fully verified using a coverage driven methodology in pseudo random simulation. The NVMe Target Core is available for integration into Altera FPGA designs to provide an industry compliant NVMe interface at PCIe Gen3, Gen2 or Gen1 interface. Some target applications include: •\tInternal connections to computer motherboards •\tM2 and M3 storage •\tSolid State Disks (SSD)

Features

    Device Utilization and Performance

    600 Mb/s serial burst, and 550 MB/s sustained; Performance is based on the type of drive used in the application. 3656 ALUTs, 658432 Block Memory Bits.

    Getting Started

    Please contact info@intelliprop.com to discuss specific needs for your project for a prompt reply.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    RTL Encrypted code; simulation script; synthesis or place & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportlinux
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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