IntelliProp NVMe-to-NVMe Bridge (IPC-NV171A-BR)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix V

Overview

The IntelliProp IPC-NV171A-BR, NVMe-to-NVMe Bridge utilizes the IntelliProp NVMe Host Accelerator Core and the IntelliProp NVMe Target Core to create an NVMe protocol bridge. The bridge is architected such that the command submissions, completion notifications and data transmissions may be either passed through without interruption or intercepted for analysis or modification. The architecture implements a ”sandbox” area in the bridge so that IntelliProp customers may implement their own custom RTL and/or firmware in the bridge. The protocol interface is compliant to the NVM Express 1.3 specification and is fully verified using a coverage driven methodology in pseudo random simulation. Applications include: High performance read/write caching; Data Deduplication; LBA Remapping; Namespace manipulation; Data encryption; Data compression; Endpoint aggregation.

Features

    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

    Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Synthesis and place and route scripts
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLinux
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated N. Altera Board Name Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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