IntelliProp NVMe-to-SATA Bridge (IPP-NV186A-BR)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria 10 SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The IntelliProp IPP-NV186A-BR is an NVMe-to-SATA Bridge that utilizes the IntelliProp NVMe Target IP Core and the IntelliProp SATA AHCI Host Core to create an NVMe-to-SATA protocol bridge. The bridge is architected such that the command submissions, completion notifications and data transmissions may be either passed through without interruption or intercepted for analysis or modification. The architecture implements a ”sandbox” area in the bridge so that IntelliProp customers may implement custom RTL and/or firmware in the bridge. The NVMe protocol interface is compliant to the NVM Express 1.3 specification and the SATA interface is compliant with the SATA 3.3 specification as defined by the Serial ATA International Organization (SATA-IO). Applications for the IPP-NV186A-BR include: High performance read/write caching ; LBA Remapping; Namespace manipulation; Data encryption/compression; Endpoint aggregation.

Features

  • Automated command submission and completion
  • Scalable I/O queue depth
  • Support for 256 outstanding I/O commands
  • Submission queue command context error prevention
  • Supports SATA AHCI 1.3.1 specification

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Synthesis and place and route scripts
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria 10
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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