IntelliProp SAS Initiator IP Core (IPC-SS105A-HI)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10

Cyclone Series: Cyclone IV

Stratix Series: Stratix IV, Stratix V

Overview

The IntelliProp IPC-SS105A-HI, SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high throughput SAS storage devices. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization and provide an industry compliant SAS 3.0 and 6.0 Gb/s interface for host designs. As with all IntelliProp cores, the IPC-SS105A-HI core is fully verified in psuedo-random simulation. Target applications for the IPC-SS105A-HI core include: Internal interconnect for workstation and server storage; Enterprise storage interconnect; HDD/SSD hot-swap environments; SAS Emulator/test boxes.

Features

    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

    Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

    IP Quality Metrics

    Basic
    Year IP was first released2008
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    RTL Encrypted code; synthesis or place & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportstandalone
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix IV, Stratix V
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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