IntelliProp SAS Initiator IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria 10 SoC

Cyclone Series: Cyclone IV

Stratix Series: Stratix IV, Stratix V


IntelliProp's SAS Initiator Core is an industry standard core that enables host designs to connect to high throughput SAS storage devices. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization. As with all IntelliProp cores, the IPC-SS105A-HI core is fully verified in psuedo-random simulation. IntelliProp's SAS Initiator core is available for integration into host side ASIC and FPGA designs to provide an industry compliant SAS 3.0 and 6.0 Gb/s interface for host designs. Some of the target applications for the IPC-SS105A-HI core are (1) Internal interconnect for workstation and server storage; (2) Enterprise storage interconnect (3) HDD /SSD hot-swap environments (4)SAS Emulator/test boxes.


    Device Utilization and Performance

    600 Mb/s serial burst, and 550MB/s sustained; Performance is based on the type of drive used in the application. 7165 LUTS, 382464 bit memory. Other FPGAs, like Arria10 GX, StratixV GX will be smaller in size.

    Getting Started

    Please contact to discuss specific needs for your project for a prompt reply.

    IP Quality Metrics

    Year IP was first released2008
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    RTL Encrypted code; synthesis or place & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportstandalone
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Arria 10, Cyclone IV, Cyclone V, Stratix IV, Stratix V
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

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