IntelliProp SAS Target IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria 10 SoC

Cyclone Series: Cyclone IV

Stratix Series: Stratix IV, Stratix V

Overview

IntelliProp's SAS Target Core is an industry standard core that enables device applications to connect to high throughput SAS storage devices. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization. As with all IntelliProp cores the SAS Target IP core is fully verified in psuedo-random simulation. Applications. IntelliProp's SAS Target IP core is available for integration into target side ASIC and FPGA designs to provide an industry compliant SAS 3.0 and 6.0 Gb/s interface. Some of the target applications include (1)\tInternal interconnect for workstation and server storage; (2) External workstation/Enterprise Storage interconnect; (3) HDD /SSD hot-swap environments; (4) Small form factor

Features

    Device Utilization and Performance

    600 Mb/s serial burst, and 550MB/s sustained; Performance is based on the type of drive used in the application. 7165 LUTS, 382464 bit memory. Other FPGAs, like Arria10 GX will be smaller in size.

    Getting Started

    Please contact info@intelliprop.com to discuss specific needs for your project for a prompt reply.

    IP Quality Metrics

    Basic
    Year IP was first released2008
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    RTL Encrypted code; synthesis or place and route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportstandalone
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Arria 10,Cyclone IV, Cyclone V, Stratix IV, Stratix V
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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