IntelliProp SATA Bridge Platform (IPP-SA143A-BR)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix IV

Overview

The IntelliProp IPP-SA143A-BR, SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with an embedded processor to handle bridging between these cores including system management interfaces outside of SATA scope. The bridging interface allows for data and command manipulation along with non-host initiated command generation and processing to the attached SATA device. The negotiated transfer rate of each SATA connection is independent of the other SATA connections allowing SATA 1.5Gb/s, SATA 3Gb/s, and SATA 6Gb/s hosts and devices to communicate at their maximum rates, or lower rates to minimize power consumption. Applications for the IPP-SA143A-BR include: controlling the flow of commands reorder of queues, for example write blocking; Encryption Bridge, Compression of data whereby less space is utilized on the drive; Allows for SATA-ATA drives to seamlessly represent themselves as SATA-ATAPI devices.

Features

    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

    Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Simulation script, sample vectors
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.