IntelliProp SATA Host App IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V


IntelliProp's SATA host IP enables host application companies to use high throughput SATA storage devices. The protocol interface is compliant to the SATA 3.3 specification as defined by SATA-IO and is fully verified in pseudo random simulation. Target applications include Enterprise storage interconnect, HDD/SSD hot-swap environments, applications requiring smaller form factor and improved performance over ATA, or any system needing to connect to a SATA storage medium.


    Device Utilization and Performance

    600 Mb/s serial burst, and 550MB/s sustained; Performance is based on the type of drive used in the application. 5511 LUTS, 131600 bit memory (on StratixIV GX). Other FPGAs, like Arria10 GX, StratixV GX will be smaller in size.

    Getting Started

    Please contact to discuss specific needs for your project for a prompt reply.

    IP Quality Metrics

    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    RTL Encrypted code; simulation script, vectors & expected results; synthesis or place & route script
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportlinux
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria II, Arria V, Arria 10, Attila Arria 10, Stratix IV, Stratix V, Cyclone IV, Cyclone V
    Industry standard compliance testing performed
    If yes, which test(s)?UNH interoperability
    If yes, on which Altera device(s)?Arria II, Stratix IV
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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