IntelliProp SATA RAID IP Core (IPC-BL109A-RD)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria 10 SoC

Cyclone Series: Cyclone V

Stratix Series: Stratix IV, Stratix V


The IntelliProp IPC-BL109A-RD, SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide higher performance access to SATA storage endpoints. RAID 0 will divide data among multiple storage endpoints providing higher system storage performance. •\tStriping (RAID 0) splits the data across multiple endpoints for greater performance. •\tCapacity (RAID 0) combines the capacity of all the endpoints using concatenated mode or RAID 0 mode. The IntelliProp RAID IP Core introduces very little latency to issue commands and to transfer data between the SATA storage devices and the backend data interface. The RAID IP Core is designed to exist within a customer’s larger design to provide RAID performance availability and capacity advantages. Applications include: combining multiple drives in parallel to increase system performance; Increase the overall capacity by combining the sizes of all the connected drives.


    Device Utilization and Performance

    Please contact IntelliProp for FPGA device specific performance and utilization information.

    Getting Started

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    IP Quality Metrics

    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Simulation script, sample vectors
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportn/a
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix V, Cyclone V
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

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