TICO Lightweight Decoder (HD/4K/8K)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

TICO compression is visually lossless lightweight compression specifically designed for the industry. This revolutionary technology is extremely tiny in FPGAs, fitting the smallest Xilinx devices, robust for real-time operation with no latency.

Features

    Device Utilization and Performance

    Depends on IP-core configuration From HD up to 4K or 8K or more. From Low frame rate to high speed Various architecture running at various frequencies

    Getting Started

    Contact intoPIX and Intel PSG for an evaluation and more technical details

    IP Quality Metrics

    Basic
    Year IP was first released2013
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    intoPIX HDK framework and reference software
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS support/
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSIM
    Hardware validated Y. Altera Board Name Stratix IV, Stratix V, Arria V, Cyclone V, Arria 10
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  Y

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