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iW-RainboW-G24M: Arria 10 SoC / FPGA System On Module
Board Image
Block Diagram
Overview
iWave’s Arria 10 SOC/FPGA System on Module is based on the Arria 10 SX/GX family device with F34 package. The module is equipped with 32-bit DDR4 memory support for HPS with optional ECC and 64-bit DDR4 support for FPGA. All the IOs and high-speed transceiver blocks will be available on the SOM board to board connector. •\tSoC/FPGA: o\tCompatible Arria10 SoC Family - SX270, SX320, SX480, SX570, SX660 o\tWith upto 660K Logic Elements, 24 High Speed Transceivers and integrated Dual Core ARM Cortex A9 @ upto 1.5 GHz/Core Hard Processor System (HPS) o\tCompatible Arria10 FPGA Family - GX270, GX320, GX480, GX570, GX660, GX900, GX1150 •\tWith upto 660K Logic Elements and 24 High Speed transceivers •\tMemory: o\t1GB DDR4 SDRAM (32bit) with ECC for HPS/FPGA (Expandable) ¹, ² o\tMicroSD Connector for HPS booting ¹, ³ o\tNAND Flash for HPS booting (Optional) ¹, ³ o\tConfiguration Flash for FPGA (Optional) o\tDDR4 RAM (64bit) from FPGA (Optional)4 •\tOther On-SOM Features: o\tJTAG Header o\tFAN Header o\tFPGA AS Header (Optional) o\tFPGA Configuration Selection Switch (Optional) •\tBoard to Board 1 Interfaces: o\tFPGA High Speed Transceivers (up to 17.4Gbps) x 18 o\tFPGA IOs & General-Purpose Clocks - Bank2A •\tUp to 46 Single Ended IOs •\tOne General Purpose Clock Input LVDS Pair/Single Ended •\tTwo General Purpose Clock Output LVDS Pairs/Single Ended o\tFPGA IOs & General-Purpose Clocks – Bank3A •\tUp to 47 Single Ended IOs •\tTwo General Purpose Clock Input LVDS Pairs/Single Ended •\tTwo General Purpose Clock Output LVDS Pairs/Single Ended •\tBoard to Board 2 Interfaces: o\tFrom HPS Block: 1, 5 •\tGigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY) •\tUSB OTG x 1 Port (through On-SOM USB ULPI PHY) •\tDebug UART (UART0) x 1 Port •\tData UART (UART1) x 1 Port (With CTS & RTS) •\tSPI x 1 Port •\tI2C x 1 Port •\tHPS GPIOs •\tHPS Warm Reset o\tFrom FPGA Block: •\tFPGA High Speed Transceivers (up to 17.4Gbps) x 6 •\tFPGA IOs & General-Purpose Clocks – Bank3B •\tUp to 24 LVDS IOs
Development Kit Software Contents
- Embedded Linux
- SD Card with pre-loaded Linux OS
- Software Documentation
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-120-3008472212413-g24m-arria-10-soc-som-brochure-r1-2.pdf | iW-RainboW-G24M: Arria 10 SoC / FPGA System On Module Brochure | 1.2 |
Board Quality Metrics
| Basic |
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|---|---|
| Latest version of Quartus supported | 17.0 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | N |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
| Parts per Million (PPM) | N/A |
| Board Policy | |
| Return Material Authorization (RMA) Policy | http://www.iwavesystems.com/support/rma.html |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. Contact iWave Systems via email at mktg@iwavesystems.com for details. |
| Conflict Mineral Policy Compliant |
NULL |
| Test Plan Summary | |
|
Contact iWave Systems via email at mktg@iwavesystems.com for details. |
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| Additional Compliance | |
| ISO 9000 & 9001; REACH compliant |
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