80186XL Processor

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

The 80186XL is a powerful 16-bit microprocessor core, executes instruction list compatible with 80186XL microprocessor. The 80186XL core has a broad set of integrated peripherals, which helps reduce system development time and cost and is compatible with wide range of compilers and debuggers. The design along with multiple peripherals can be fit into single FPGA.

Features

    Device Utilization and Performance

    Altera Cyclone IV E Logic Element combinational - 8693 Logic Element Registers - 3189 Embedded Multipliers 9 bit Elements - 4

    Getting Started

    1. Compatible with Intel 80186XL instruction set 2. High FPGA integration enables lower BOM cost and smaller board design. 3. Supports retarget and merge external peripherals and traditional custom old ASICs. 4. Quick migration of 80186XL based designs to an FPGA platform. 5. Replacement for 80186XL processor and ASICs.

    IP Quality Metrics

    Basic
    Year IP was first released2008
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLINUX
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim DE 10.2
    Hardware validated Y. Altera Board Name Any Altera Development kit
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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