8251 Serial Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

8251 Serial Controller is an USART with support for asynchronous communication only. This controller converts parallel data from the processor to serial data and transmits it and converts the serial received data into parallel data for the processor to read.

Features

    Device Utilization and Performance

    Altera Cyclone IV E Logic Element combinational - 164 Logic Element Registers - 147

    Getting Started

    1. Uses as a peripheral device of microcomputer system 2. Configurable for ease of use 3. Compatible with 8251 and uPD71051 4. Programmable baud rate generator

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLINUX
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim DE 10.2
    Hardware validated Y. Altera Board Name Any Altera Development kit
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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