8530 Multi-Protocol Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

8530 MPSC Controller (Multi-Protocol Serial Communication Controller) is a general-purpose communication controller which consists of two sets of bi-directional parallel / serial converter circuits for data communication.

Features

  • Hardware features - Transmit buffer (2 Byte Depth) & Receive buffer (4 Byte Depth) & Interrupt control function
  • Communication protocol features - Start-stop synchronization & Character oriented protocol (COP) - Mono-sync, Bi-sync, External sync
  • Encode/decode of NRZ (Non-Return to Zero)
  • Encode/decode of NRZI (Non-Return to Zero Inverted) & Encode/decode of FM (Frequency Modulation)
  • Decode in Manchester mode

Device Utilization and Performance

Altera Cyclone IV E Logic Element combinational - 5399 Logic Element Registers - 1989

Getting Started

1. Controller has facilities for modem controls in both channels 2. Controller modem signals are not used then they can be used as general purpose I/O 3. Compatible with uPD72001 and 85C30 4. Controller supports all three serial protocols (UART, Mono-Sync, Bi-Sync, HDLC and SDLC)

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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