DMA Core for PCIe Hard IP

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V


iWave provides the user application for PCI-e target bridge to access the control & status registers of custom logic and data transfers to custom logic. In addition multi-channel scatter gather DMA core provides the hardware assisted high speed data transfers between the PCI-e and custom logic. This IP core simplifies the integration of PCI-e hard macro controller with custom logic.


    Device Utilization and Performance

    Altera Arria II GX Logic Element combinational - 2889 Logic Element Registers - 2969 Embedded Multipliers 9 bit Elements - 13

    Getting Started

    1. Core reduces the design development cycle as well as design complexity 2. TLP Encoding &Decoding and completion packet handling simplifies integration of customlogic with PCI-e 3. Custom logic need not to interact with PCI-e Hard IP 4. Easy to use scatter gather DMA controller

    IP Quality Metrics

    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLINUX
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Simulators supportedModelSim DE 10.2
    Hardware validated Y. Altera Board Name iWave's Altera Cyclone V SoC Development Platform
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.