PCI Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

PCI Controller provides an interface between the PCI bus and user interface. PCI core interface is processor independent, enabling an efficient transition to future processor generations and use with multiple processors.

Features

  • 64-bit, 33/66MHz PCI interface
  • Supported initiator commands and functions:Parity generation, parity error detection
  • Supported target commands and functionsType 0 configuration space header
  • PCI Configuration base registers are configurable from header file

Device Utilization and Performance

Altera Cyclone IV E Logic Element combinational - 510 Logic Element Registers - 456

Getting Started

1. Core enables concurrent operation of the local bus with the processor/memory sub system 2. 64-bit extension doubles the bus bandwidth 3. Compliant with PCI Specification 2.3 4. Separate initiator and target functional blocks.

IP Quality Metrics

Basic
Year IP was first released2009
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  Y

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