SD / SDIO / MMC Host Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Memory Interfaces for ALTMEMPHY

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

iW-SD Controller interfaces SD / MMC / SDIO card to any processor with a generic interface. The interface towards the SD card is realized by the SD protocol implemented in the controller.

Features

  • Compliant with SD Host Controller Standard Specification Version 2.0
  • Compliant with SD Physical Layer Specification Version 2.0
  • Compliant with SDIO Specification 2.0 & Compliant with eMMC Specification Version 4.41
  • Supports 1-bit,4-bit SD/eMMC modes and 8-bit eMMC modes & Supports SD Card Detection input pin
  • Cyclic Redundancy Check (CRC) for command and data & Supports both single block and multi block data transfer.

Device Utilization and Performance

Altera Cyclone IV E Logic Element combinational - 1420 Logic Element Registers - 1243 Embedded Multipliers 9 bit Elements -4

Getting Started

1. To enable memory storage (SD/MMC memory card) and Input/output (SDIO card) features in the product 2. Host controller for SD/SDIO cards where the processor in the platform doesn’t support SD/SDIO interface 3. To increase the number of SD/SDIO interface support in the platform 4. Compliant with SDIO specification version 2.0, SD specification version 2.0, MMC specification version 4.41 5. Controller provides simple slave interface for control & status access and master interface for DMA data transfer

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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