Supported Device Family:
iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0. The core supports 32 bit AHB LITE Host interface working at SOC interface frequency. The Host interface is compatible with the standard register set for the host controller as per SD host controller specification Version 3.0.
- Compliant with SD specification version 3.0 & Supports 32 bit AHB LITE synchronous Host interface working at SOC interface frequency.
- 1-bit/4-bit modes of SD/SDIO supported. & One data Transmit FIFO with 32-bit write width and 256 depths.
- SDR50 – SDR up to 100MHz 1.8V signaling & DDR50 – DDR up to 50MHz 1.8V signaling
- One data Receive FIFO with 32-bit read width and 256 depths. & SDIO Interrupts, Suspend/Resume Operation and SDIO Read Wait Operation are supported.
- Command buffers to store command index and argument. & Timeout monitoring for response and data operation.
IP Quality Metrics
|Year IP was first released||2011|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||N|
|Driver OS support||LINUX|
|IP-XACT Metadata included||N|
|Simulators supported||ModelSim DE 10.2|
|Hardware validated||Y. Altera Board Name Any Altera Development kit|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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