SDIO to UART Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.

Features

    Device Utilization and Performance

    Altera Cyclone IV E Logic Element combinational - 1,902 Logic Element Registers - 1,157 Memory Bits - 33,024

    Getting Started

    1. IP can be quickly customized to implement the SDIO to other devices like USB, PHS, Bluetooth and Wi-Fi etc. 2. SDIO interface supported by the bridging IP enables a low-cost and small size implementation.

    IP Quality Metrics

    Basic
    Year IP was first released2012
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLINUX
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim DE 10.2
    Hardware validated Y. Altera Board Name iWave's Altera Cyclone V SoC Development Platform
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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