SDXC Host Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Memory Models

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0. The core supports 32 bit AHB LITE Host interface working at SOC interface frequency. The Host interface is compatible with the standard register set for the host controller as per SD host controller specification Version 3.0.

Features

    Device Utilization and Performance

    Altera Cyclone IV E Logic Element combinational - 3570 Logic Element Registers - 1301 Embedded Multipliers 9 bit Elements -4

    Getting Started

    1. To give the latest SD specification version support SD 3.0 2. To enable memory storage (SDXC memory card) and input/ output (SDIO card) features in the product 3. Controller supports standard register set for the host controller 4. Core offers UHS-I mode of operation

    IP Quality Metrics

    Basic
    Year IP was first released2011
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLINUX
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim DE 10.2
    Hardware validated Y. Altera Board Name Any Altera Development kit
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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