sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.
1. This intellectual property core can be implemented on any transceiver based Xilinx/Altera/Lattice FPGAs. 2. Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2003 standard. 3. The Serial FPDP standard supports three data rates: 1.0625 Gbaud, 2.125 Gbaud, and 2.500 Gbaud.
IP Quality Metrics
|Year IP was first released||2011|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Parameterization GUI allowing end user to configure IP||Y|
|IP core is enabled for OpenCore Plus Support||Y|
|Software drivers provided||N|
|Driver OS support||LINUX|
|IP-XACT Metadata included||N|
|Simulators supported||ModelSim DE 10.2|
|Hardware validated||Y. Altera Board Name Stratix IV GX|
|Industry standard compliance testing performed||N|
|If No, is it planned?||Y|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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