Display Interface Module

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The Display Interface module is a core module that provides the interface directly to an LCD module, or through and external triple DAC or HDMI transmitter, directly to any standard video display. Small and efficient and simple to use interfaces and driver model make it easier than ever to get output from your FPGA to the screen.

Features

    Device Utilization and Performance

    ~3k LEs ~22 MK9 Memory Blocks (dependent on line prefetch buffer size) ~15 mults (Can use logic for these if needed)

    Getting Started

    The core design can be integrated and tested using the following steps: 1. Create buffers/RAMs in the target device family for the line buffers and add them to the generic memory vhd file. Same for the cursor cache if needed. 2. Instantiate the core into the FPGA design connecting to specific Qsys Avalon interfaces depending on functions needed and to the video interface/display bus. 3. If needed adjust output video HW bus to your display's needs. The output from the core can easily manipulated into various interface standards by the end developer. Custom interfaces can be developed by Tectonics. Please email engineering@logic-tectonics.com with questions. 3. Set the generics on the core file according to functions needed/used. 4. import the graphics library files into the nios SW project 5. Initialize a frame buffer using the library 6. Initialize a font and then use printf() function to print to the frame buffer 7. Add other calls from the library as needed.

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportflexible
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAldec, Modelsim, other
    Hardware validated Y. Altera Board Name Terasic DE-115
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.