The Display Interface module is a core module that provides the interface directly to an LCD module, or through and external triple DAC or HDMI transmitter, directly to any standard video display. Small and efficient and simple to use interfaces and driver model make it easier than ever to get output from your FPGA to the screen.
The core design can be integrated and tested using the following steps: 1. Create buffers/RAMs in the target device family for the line buffers and add them to the generic memory vhd file. Same for the cursor cache if needed. 2. Instantiate the core into the FPGA design connecting to specific Qsys Avalon interfaces depending on functions needed and to the video interface/display bus. 3. If needed adjust output video HW bus to your display's needs. The output from the core can easily manipulated into various interface standards by the end developer. Custom interfaces can be developed by Tectonics. Please email firstname.lastname@example.org with questions. 3. Set the generics on the core file according to functions needed/used. 4. import the graphics library files into the nios SW project 5. Initialize a frame buffer using the library 6. Initialize a font and then use printf() function to print to the frame buffer 7. Add other calls from the library as needed.
IP Quality Metrics
|Year IP was first released||2015|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||N|
Customer deliverables include the following:
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||N|
|Software drivers provided||Y|
|Driver OS support||flexible|
|IP-XACT Metadata included||N|
|Simulators supported||Aldec, Modelsim, other|
|Hardware validated||Y. Altera Board Name Terasic DE-115|
|Industry standard compliance testing performed||N|
|If No, is it planned?||N|
|IP has undergone interoperability testing||N|
|Interoperability reports available||N|
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