HDMI 2.0 IP

Block Diagram

Solution Type: IP Core

End Market: Consumer, Medical

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: HDMI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Stratix Series: Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

HDMI 2.0 IP provides transmit/receive functions of HDMI 2.0 standard for Intel FPGA. Its maximum transfer rate is 18 Gbps enabling to transmit and receive up to RGB 24 bit 4k2k@60p video. Users can bring their HDMI 2.0 compliant products to market very quickly and easily.

Features

    Device Utilization and Performance

    Refer to https://www.m-pression.com/solutions/hardware/hdmi

    Getting Started

    Refer to https://www.m-pression.com/solutions/hardware/hdmi

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNo
    Implementation
    User InterfaceOther: Original
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim/QuestaSim
    Hardware validated Y. Altera Board Name Arria 10 GX Devkit, Nitro, Arria V GX Starter Kit
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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