IEEE1588 Protocol Stack Package

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Industrial

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Cyclone Series: Cyclone IV, Cyclone V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

IEEE1588 Protocol Stack Package complies with IEEE1588 standard and achieves high precision time synchronization with accuracy of 100 nanoseconds or lower. In addition to IEEE1588-2008 compliance, this package is also compliant with SMPTE2059 which is a profile for broadcast equipment. IEEE1588 is a standard for time synchronization scheme between network-connected devices.

Features

  • IEEE1588 Version2
  • Ordinaly Clock. Master/Slave
  • Support Default Profile and ST2059 Profile

Device Utilization and Performance

Device Utilization Cyclone V implementation: ALMs (1271.2), DSP Blocks (22) NiosII FW size: 32K

Getting Started

Please contact Macnica for more information

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportMpression Scorpius (RTOS)
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedNo
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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