SLVS-EC RX IP

Block Diagram

Solution Type: IP Core

End Market: Consumer, Industrial, Medical

Evaluation Method: OpenCore Plus

Technology: Interface Protocols

Arria Series: Arria 10, Arria 10 SoC

Cyclone Series: Cyclone V, Cyclone V SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

SLVS-EC Rx IP provides SLVS-EC interface for Intel FPGA to receive image sensor data. SLVS-EC is Sony’s upcoming high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology, so that it makes a board level design very easy in terms of high-speed and long distance transmission.

Features

  • Compliant with SLVS-EC Specification Version 1.2
  • Supports various functions defined by the SLVS-EC Link layer
  • Supports Byte-to-Pixel conversion for various lane-configurations
  • Supports Header analysis and Payload error detection/correction

Device Utilization and Performance

Refer to https://www.m-pression.com/solutions/hardware/slvs-ec-rx-ip

Getting Started

Refer to https://www.m-pression.com/solutions/hardware/slvs-ec-rx-ip

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNo
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim/QuestaSim
Hardware validated Y. Altera Board Name Arria 10 GX Devkit, Nitro
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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