V-by-One HS IP

Block Diagram

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Supported Device Family: 

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Overview

V-by-One HS IP is an IP to achieve V-by-One HS high-speed video interface technology. V-by-One HS is a standard for next-generation high-speed interface technology developed by THine Electronics for image and video equipment requiring higher frame rates and higher resolutions. Implementing the V-by-One HS IP in Intel FPGA reduces the number of signals compared with conventional LVDS interfaces, which greatly reduces product cost.

Features

    Device Utilization and Performance

    Refer to https://www.m-pression.com/solutions/hardware/v-by-one-hs-fpga-solution

    Getting Started

    Refer to https://www.m-pression.com/solutions/hardware/v-by-one-hs-fpga-solution

    IP Quality Metrics

    Basic
    Year IP was first released2013
    Latest version of Quartus supported16.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNo
    Implementation
    User InterfaceOther: Original
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim/QuestaSim
    Hardware validated Y. Altera Board Name Cyclone IV GX Devkit/Stratix IV Devkit/Arria V GX Starterkit/Nitro/Stratix V Devkit/Arria 10 GX Dev
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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