IEEE 802.3 Clause 74 FEC IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Error Detection and Correction

Stratix Series: Stratix IV

Overview

The Forward Error Correction (FEC) IP core is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 100GBASE-R PHYs) of the IEEE 802.3-2008/IEEE 802.3ba-2010 specifications. The Cyclic code (2112, 2080) FEC block lies between PCS and PMA sublayers and provides coding gain to increase the link budget and BER performance.

Features

    Device Utilization and Performance

    See datasheet for details.

    Getting Started

    The FEC IP core is provided as two blocks, an encoder and a decoder, as an implementation of the error correction algorithm for a 66-bit interface, i.e. 66-bit in and 66-bit word out.

    IP Quality Metrics

    Basic
    Year IP was first released2010
    Latest version of Quartus supported16.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    See datasheet
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Direct parallel
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name Custom Stratix IV board
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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