Ultra-Low Latency 25Gb/s Ethernet IP Solution

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Arria 10

Stratix Series: Stratix V


Supported Device Family: 

Solution Type: 


This 25Gbps 64-bit Ethernet IP solution offers a fully integrated IEEE P802.3by compliant package for NIC (Network Interface Card) and Ethernet switching applications. This ultra-low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications.


  • Round Trip Latency of 59.6ns + Device Specific Transceiver Latency
  • Ultra-Low latency MAC; Tx = 17.4ns , Rx = 17.4ns; (64-bit user interface mode)
  • Ultra-Low latency PCS; Tx = 12.4ns , Rx = 12.4ns; (64-bit user interface mode)
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for external module and optical module status/control

Device Utilization and Performance

See datasheet for details

Getting Started

A complete reference design using a L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference design’s hardware elements through a UART interface (a PCIe option is also available). An application (with optional basic Linux PCIe driver/API) is also provided for memory mapped read/write access to the internal registers.

IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
See datasheet for details
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Custom Arria 10 and Stratix V boards
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  Y

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