The Ensemble OpenVPX with 4th Generation Intel Quad-Core i7 processor (Haswell mobile class) LDS6525 module combines a powerful mobile class Intel Quad-Core processor, firmware upgradable FPGA (Stratix 5 GX) implemented switch fabrics for unsurpassed fabric data rates, and configurable mezzanine I/O in a single 6U OpenVPX slot. The LDS6525, provides a next-generation architecture that balances the computational capabilities of the AVX2-enabled Core i7 processor with Gen 2 Serial RapidIO or 10 Gigabit Ethernet data paths. The combination provides a powerful and scalable computing architecture that is well aligned with high-end radar, electronic warfare and image processing applications. Intel 4th Generation Core i7 Haswell Mobile-Class Processor. At the heart of the LDS6525 is the Intel 64-bit 4th Generation Core i7-4700EQ processor, running at up to 2.4 GHz. This processor includes Advanced Vector Extensions-2 (AVX2) instruction set which doubles the width of the processor's SIMD The 4700EQ includes a large 6 MB cache shared between the cores, allowing many high-performance calculations to remain cache resident. This accelerates processing by eliminating the potential latency required to access DRAM to fetch upcoming data. The processor supports dual high speed DDR3-1600 memory controllers, providing up to 25 GB/s of raw memory bandwidth. 8 GB of DDR3-DRAM with ECC support is populated on the LDS6525.
- OpenFDK FPGA Development Kit
- System Verification Environment (SVE)
- OpenCL support
- Linux support package / board support package
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)
|Return Material Authorization (RMA) Policy||A Return Material Authorization Number (RMA#) is required to return any product sold by Mercury Systems (MRCY). An RMA# can be requested by completing the RMA Request on support.mrcy.com|
|CE Compliant||N. Military grade equipment|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
Simulation and Verification Environment (SVE) that allows complete end-to-end simulation and design verification for Mercury FPGA-based systems. It is designed to enable application developers to quickly model and verify application logic, dramatically reducing time to market.
|ISO 9000 & 9001
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