Mercury Ensemble LDS6526 OpenVPX Xeon D server

Board Image

Block Diagram

Board Category: COTS

Components & Interface: Industry Standard: Ethernet, RS232, USB Device

End Market: Computer & Storage, Industrial, Military

Technology: DSP

Board Feature: General User IO: LED

Arria Series: Arria 10: Arria 10 GX

Overview

The Ensemble LDS6526 processing blade seamlessly integrates the latest Intel Xeon processor D system-on-a-chip (SoC) product family (formerly codenamed "Broadwell DE"), the versatility and performance boost of software-defined off-load processing with built-in, double-bandwidth sensor I/O capability into a powerful 6U form factor blade for streaming signal processing applications. Mercury's software-defined, FPGA-based protocol offload engine technology (POET) combined with Altera's latest Arria 10 device effortlessly deliver twice the sensor I/O bandwidth than any other OpenVPX blade with four channels of I/O that can be routed to either the processor or data plane. This innovative embedded technology is switch fabric-agnostic and runs 40Gb/s Ethernet or many other protocols at full speed.

Order Information

Ordering Code
Pricing
Buy
910-56112-XX $Contact UsBuy Now

Development Kit Hardware Contents

  • n/a

Development Kit Software Contents

  • Linux support package / board support package
  • System Verification Environment (SVE)
  • OpenCL support
  • OpenFDK FPGA Development Kit

Support Document

File Name
Description
Version
doc-us-dsnbk-277-4604092206-lds6526.pdfoverview0

Board Quality Metrics

Basic
Latest version of Quartus supported 15.1
Required Collateral Available
User Guide Y
Board Schematics N
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

0
Parts per Million (PPM)
0
Board Policy
Return Material Authorization (RMA) Policy A Return Material Authorization Number (RMA#) is required to return any product sold by Mercury Systems (MRCY). An RMA# can be requested by completing the RMA Request on support.mrcy.com
Compliance
RoHS Compliant N
CE Compliant N. Military grade equipment
Conflict Mineral Policy Compliant
Y
Test Plan Summary

Simulation and Verification Environment (SVE) that allows complete end-to-end simulation and design verification for Mercury FPGA-based systems. It is designed to enable application developers to quickly model and verify application logic, dramatically reducing time to market.

Additional Compliance
ISO 9000 & 9001; ITAR (International Traffic in Arms Regulation)

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.