Avalon Mobile DDR Memory Controller IP Core

Block Diagram

Solution Type: Qsys Component

End Market: Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: SDRAM

Cyclone Series: Cyclone IV

MAX Series: MAX V

Stratix Series: Stratix IV

Overview

The Microtronix Avalon Mobile DDR SDRAM Memory Controller IP Core is designed for building high-performance Avalon-MM / Avalon-ST multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices lowering your production cost, and saving you money.

Features

    Device Utilization and Performance

    Device utilization: SDRAM Controller - 700 LE, Avalon Random Port - 500 LE, Avalon Burst Port 500 LE Memory performance: Arria II GX - 200MHz, Cyclone IV - 167MHz, Stratix IV - 200MHz

    Getting Started

    Reference designs are available for Altera development boards.

    IP Quality Metrics

    Basic
    Year IP was first released2007
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportNot applicable
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim
    Hardware validated Y. Altera Board Name Cyclone III IV, Arria IV GX and Stratic IV GX Development bolards
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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