Avalon Multi-Port SDRAM Memory Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Broadcast, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: SDRAM

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Overview

The Microtronix Avalon Multi-port SDRAM Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money. The Avalon-MM slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.

Features

    Device Utilization and Performance

    SDRAM Controller: 700 LE's Avalon Random Port: 500 LE's (per port) Avalon Burst Port: 500 LE's (per port) Up 333 MHz DDR2 clock rates.

    Getting Started

    Quartus II reference designs are supplied for a number of Altera development boards.

    IP Quality Metrics

    Basic
    Year IP was first released2007
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportNone required
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSIM
    Hardware validated Y. Altera Board Name Arria GX and Stratix III Dev Kits
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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