I2C Master-Slave-PIO IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Basic Functions: Configuration and Programming

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The Microtronix I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I2C Master/Slave core provide a generic memory-mapped bus interface. Also designed as an Altera Qsys component, it integrates easily into any Qsys generated system using an Nios II Avalon bus.

Features

    Device Utilization and Performance

    Requires 300 LE's for Avalon Master/Slave and 100 LE's for PIO function.

    Getting Started

    Reference designs are supplied to demonstrate the use of the IP Core.

    IP Quality Metrics

    Basic
    Year IP was first released2010
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Source code optional
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportNot applicable
    Implementation
    User InterfaceAvalon-MM
    IP-XACT Metadata includedY
    Verification
    Simulators supportedYes
    Hardware validated Y. Altera Board Name Cyclone V SoC, Arria IV GX, Arria V, Stratix IV and Stratix IV GX DE4 Dev Kit
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?I2C components
    If yes, on which Altera device(s)?Cyclone V SoC
    If Yes, date performed
    04/15/2015
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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