Lancero - Scatter-Gather DMA Engine for PCI Express

Block Diagram

Solution Type: Qsys Component

End Market: Computer & Storage, Consumer, Industrial, Medical, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Microtronix Lancero Scatter-Gather DMA Engine for PCI Express provides either a Target Bridge or a Descriptor Bridge SGDMA solution for PCI Express endpoints. The IP connects seamlessly to Altera PCI Express Hard IP cores, providing a transparent high-speed data path over PCI Express. Driver packages are available for Windows, Linux, QNX and Apple OSX.

Features

  • Easily connect logic and high-speed I/O peripherals to PCI Express
  • Scatter-Gather DMA Engine supports Avalon Streaming burst access devices
  • SGDMA controller transfers data directly to/from Linux/Windows User Applications
  • Zero host CPU overhead: SGDMA transfers eliminates need for duplicate in-kernel transfers
  • Supports asynchronous and multi-threaded I/O to completely remove inter-transfer latencies

Device Utilization and Performance

Device utilizations: PCIe Bridge DMA - Cyclone IV GX (x1/x4 lane) - 1354 LE, Arria II GX/Stratix IV GX (x1/x4 lane) - 592 LE, Arria II GX/Stratix IV GX (x8) - 680 LE PCIe SG DMA - Cyclone IV GX (x1/x4 lane) - 5905 LE, Arria II GX/Stratix IV GX (x1/x4 lane) - 2594 LE, Arria II GX/Stratix IV GX (x8) - 2834 LE I/O Performance: Gen1: x1/x8: 200MBps/1650MBps, Gen2: x1/x8 440MBps/3200MBps

Getting Started

Complete Reference Designs are supplied for a wide range of Altera Development boards. The Lancero IP package includes complete driver for Linux, QNX and Windows.

IP Quality Metrics

Basic
Year IP was first released2010
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Complete driver source
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux, QNX, Windows
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Cyclone V SoC, Arria II GX, Arria V and Stratix IV GX (Terasic) DE4 Dev Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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