Streaming Multi-port SDRAM Memory Controller

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Microtronix Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory. The core integrates: a burst memory controller core, a port arbitrator and intelligent look-ahead FIFO controller into one easy-to-use core. It supports SDR, DDR, DDR2 and Mobile DDR memory devices in a single IP Core assuring designers of a smooth low-risk migration path with changing SDRAM technology. The core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system. Using the intuitive Microtronix GUI interface, with a few clicks of a mouse, designers can create a multi-port system, a design task which would normally take several man-months of effort!

Features

  • Supports 10 local bus RD/WR interface ports
  • Provides simple target and register interfaces
  • Reduces the memory design process to a two-step compilation process
  • FIFO port interface enables independent clock domains for memory and local buses
  • Source-synchronous date capture design

Device Utilization and Performance

SDRAM Controller: 745LE's Write Port: 300 LE's (per port) Read Port: 100 LE's (per port)

Getting Started

Quartus II Reference Designs are supplied for a variety of Altera Development boards.

IP Quality Metrics

Basic
Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportNone required
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSIM
Hardware validated Y. Altera Board Name Arria GX Dev Kit, Stratix III Dev Kit, Terasic DE4
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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