Gen4 PCI Express Root Complex Controller with SRIOV

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Stratix Series: Stratix V

Overview

MOBIVEIL's PCI Express Root Complex Controller is a highly flexible and configurable design targeted for implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.

Features

    Device Utilization and Performance

    Maximum Link Width (x1, x2 x4, x8, x16) Maximum TLP data payload size supported (128B to 4KB) Data Path Widths (32, 64, 128, 256bit) 8-bit, 16-bit, 32-bit and 64-bit PIPE interface Transmit Retry/Receive Buffer size Number of Virtual Channels Inclusion of specific sublayers etc. ASPM L1 / Wake support, Auxiliary power support

    Getting Started

    www.mobiveil.com/interfaces/

    IP Quality Metrics

    Basic
    Year IP was first released2005
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportLinux
    Implementation
    User InterfaceAXI; Other: Packet interface
    IP-XACT Metadata includedY
    Verification
    Simulators supportedVCS, NC, Questa
    Hardware validated Y. Altera Board Name Stratix V Reference kit
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PCISIG
    If yes, on which Altera device(s)?Stratix V
    If Yes, date performed
    01/01/2014
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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