Mobiveil NVMe Controller - UNEX

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage

Evaluation Method: Source Code

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix 10, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

Mobiveil's Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions that unlock the current and future potential of PCIe-based SSDs. The UNEX controller core efficiently supports multi-core architectures ensuring thread(s) may run on each core with their own queue and interrupt without any locks required. It provides support for end-to-end data protection, security and encryption as well as robust error reporting and management capabilities. The controller architecture is carefully tailored to optimize link and throughput utilization, latency, reliability, power consumption, and silicon footprint.

Features

  • Compliant to NVM Express 1.3 specification
  • Supports Multi-port Configuration for Multipath IO support
  • Support for configurable number of IO Queues
  • Support for configurable Queue depth
  • Support for Round Robin or Weighted Round Robin with Urgent Priority arbitration mechanism

Device Utilization and Performance

Contact ip@mobiveil.com for size information

Getting Started

Contact ip@mobiveil.com

IP Quality Metrics

Basic
Year IP was first released2013
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows10, Linux
Implementation
User InterfaceAXI; Other: Avalon ST
IP-XACT Metadata includedN
Verification
Simulators supportedVCS. NC, Questa
Hardware validated Y. Altera Board Name Stratix V, Arria10GX and Arria10SoC boards
Industry standard compliance testing performed
Y
If yes, which test(s)?UnH
If yes, on which Altera device(s)?Stratix V
If Yes, date performed
02/26/2014
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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