32 Gigabit Fibre Channel FC-1

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Test & Measurement, Wireline

Evaluation Method: OpenCore

Technology: Interface Protocols: Communications

Stratix Series: Stratix V


The 32 FC-1 Core provides a generic solution 28.050Gbps (32GFC) Fibre Channel applications. The core is designed to support standard Fibre Channel applications such as point-to-point and fabric interconnect. On the System side, the Core implements a 128-Bit XGMII interface and can be connected 16/32GFC-2 Layer provides services such as CRC generation / check, generate Fibre Compliant frames and maintains buffer-to-buffer credit and necessary Fibre Channel timers. The Core implements the standard Reed Solomon Forward Error Correction (RS-FEC) RS(528, 514) function and word alignment function.


    Device Utilization and Performance

    ALMs: 19700 M20Ks: 20

    Getting Started

    Contact MorethanIP

    IP Quality Metrics

    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNo
    User InterfaceOther: xGMII
    IP-XACT Metadata includedN
    Simulators supportedModelsim, Questa, VCS
    Hardware validated N. Altera Board Name Customer HW
    Industry standard compliance testing performed
    If No, is it planned?N
    IP has undergone interoperability testing
    Interoperability reports available  N

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