GigaChip Interface

Block Diagram

Solution Type: IP Core

End Market: Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Arria 10

Stratix Series: Stratix IV, Stratix V

Overview

The GigaChip� Interface is a reliable serial chip-to-chip transport protocol that operates over Optical Internetworking Forum (OIF) standard CEI SerDes and achieves 90% efficiency. The protocol, called the GigaChip Interface (GCI), can be scaled to 1, 2, 4 or 8 SerDes lanes as well as multiples of 8s. It targets computational and memory solutions with serial interfaces for networking equipment such as MoSys� Bandwidth Engine� family of ICs and MoSys Programmable Search Engine (PSE). Operating on existing devices with 16 lanes at 15 Gbps, GCI provides enough bandwidth to support 4.5B read/write transactions and sufficient bandwidth to buffer full duplex 200GE. Doubling the pins or doubling the line rate (30Gbps) achieves full duplex 400GE.

Features

    Device Utilization and Performance

    The GigaChip Interface (GCI) uses a fixed-size 80-bit frame, consisting of 72-bit payload, 6 bits of CRC and 2 control bits, providing 90% transport efficiency. Each lane is scrambled with a pseudo-random bit sequence, providing sufficient transition density and DC balance for reliable, high-speed serial communications without the overhead of 8b/10b encoding. Commands are defined as 36-bit half words and sent to the device in pairs within the 72-bit payload.

    Getting Started

    The GigaChip Interface (GCI) was specifically designed for its intended applications. Parallel memory interfaces provide high bandwidth and low latency, but their large numbers of signals consume package balls and board routing resources, and their very tight routing restrictions constrain board layout. Serial interfaces like Interlaken provide low ball count and flexible board layout, but they have high protocol overhead and high latency because they can support long routing distances, variable length packets, multiple logical channels, multiple priority levels, routing to multiple destinations, and multiple message types. Also, they provide error detection but no automatic recovery from errors. GCI is a serial interface that leaves out features that are not needed for point-to-point communication of fixed-size frames over short distances. Therefore, it achieves very low latency, high bandwidth, and high utilization (90% efficiency) for small frames while maintaining high reliability.

    IP Quality Metrics

    Basic
    Year IP was first released2010
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    GigaChip Interface Specification, RTL code, license agreement
    Parameterization GUI allowing end user to configure IPY
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportLinux, Windows
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedSynopsys VCS, Mentor Graphics ModelSim, Cadence NC Verilog
    Hardware validated Y. Altera Board Name Stratix IV, Stratix V, Arria 10
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?HTOL,ESD,HAST,HTSL,Latchu
    If yes, on which Altera device(s)?Arria 10 for GCI testing
    If Yes, date performed
    04/01/2016
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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