HDMI Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

MRA Digital’s HDMI/DVI RX PHY core provides an easy solution to implement HDMI/DVI Receiver inside Altera FPGA devices. By integrating HDMI receiver inside FPGA eliminates the need for an external HDMI Receiver chip thus providing significant cost saving as well as saves PCB real estate. MRA HDMI RX core uses FPGA regular I/Os to implement high speed serial lanes making it possible to use low cost FPGA devices in high speed applications. Alternatively, on Altera high-end FPGA devices by implementing HDMI interface using regular I/Os provides savings in Giga bit transceiver resources which can be employed to implement other high speed interfaces.

Features

  • HDMI/DVI Tx - 600 LE's ... HDMI/DVI Rx - 700LE's
  • Does NOT require High Speed Tranceivers
  • FPGA Technology Independent
  • Up to 2K & 4K Resolutions
  • Support for Multiple Color Space

Device Utilization and Performance

The FPGA resource estimate for the HDMI RX PHY core on MAX10 device is as follows: -FPGA I/O Pins: 8 -Logic Cells: 679 -Dedicate Logic Registers: 560 -Memory Bits: 480 -M9Ks: 3 -PLL: 1 -DSP Elements: 0 The resource consumption is expected to be similar on other Altera devices.

Getting Started

MRA has an HDMI demo platform as well as a daughter card for the MAX10. Please contact MRA for more details.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNIOS
Implementation
User InterfaceOther: n/a
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim Altera Edition
Hardware validated Y. Altera Board Name MAX10 Development Kit + Daughter Card
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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