Myrtle accelerates performance critical workloads on FPGAs and has realized multiple proprietary deep learning networks as silicon designs, so that they execute at a latency and power point that makes them usable in real-world situations. Myrtle is currently targeting its automated design technology at inference workloads in data centers and is also involved in a major collaboration to address the safety and verification challenges for deep learning networks used in autonomous vehicles. Myrtle has significantly accelerated the time-to-market for FPGA designs by automating the translation of AI network designs using compiler technology targeting the Intel® Arria® 10 FPGA. Trained, high level algorithms, specified in a wide range of network descriptor formats – Torch, Caffe etc. are compiled and mathematically optimised, directly to VHDL to produce efficient, low latency designs. In cases where proprietary non-standard, deep learning layers are used these first need to be implemented
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