EtherCAT MASTER IP

Block Diagram

Solution Type: IP Core

End Market: Industrial

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Cyclone Series: Cyclone V SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

NDR has acquired the technology of EtherCAT Hardware Master owned by a major industrial machinery manufacturer, and developed a SoC FPGA IP so that more users can flexibly use it. The FPGA hardware communication engine reduces the software load by providing a fast communication interval and stable communication cycle. The resources required for CPU processing can be allocated to applications and hence the software load fluctuations (including the addition of functions) will not affect the communication. In addition, it is also possible to mount directly to the proprietary boards using the IP.

Features

    Device Utilization and Performance

    Contact info-fpga@ndr.co.jp

    Getting Started

    Contact info-fpga@ndr.co.jp

    IP Quality Metrics

    Basic
    Year IP was first released2016
    Latest version of Quartus supported16.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    N
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVHDL
    Software drivers providedY
    Driver OS supportLinux,uITRON
    Implementation
    User InterfaceAXI; Avalon-MM
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim*
    Hardware validated N. Altera Board Name NULL
    Industry standard compliance testing performed
    N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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