CSI-2 Controller Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Interface Protocols: Serial

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

The CSI-2 Controller Core is part of Northwest Logic MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use. The core implements all three layers defined by the CSI-2 Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management, and is fully compliant with the CSI-2 specification. Separate Transmit (TX) and Receive (RX) versions of the core are provided. The core supports 1 to 4 data lanes at rates 1.5+ Gbps and all data types. The core's local interface is an easy-to-use pixel-based interface (single, double, and quad pixel wide). The core is delivered fully integrated and verified with the user's target MIPI PHY. The core is also provided with the MIPI CSI-2 Testbench which provides a MIPI CSI-2 bus functional model. Contact Northwest Logic for more information.

Features

  • Transmit and receive versions available
  • 1-4 data lane support
  • Fully CSI-2 Specification compliant
  • Supports all data types
  • High-performance, easy-to-use core

Device Utilization and Performance

Contact Northwest Logic

Getting Started

Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

IP Quality Metrics

Basic
Year IP was first released2010
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Expert technical support
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Pixel, Video, Packet
IP-XACT Metadata includedN
Verification
Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.