DDR2 SDRAM Controller Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: SDRAM

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V

Stratix Series: Stratix V

Overview

Northwest Logic's Double Data Rate 2 (DDR2) SDRAM Controller intellectual property (IP) core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR2 SDRAM devices. The core also performs all initialization, refresh and power-down functions. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time. The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. Add-on cores such as a multiport front-end and reorder core can be optionally delivered with the core. Contact Northwest Logic for more information.

Features

    Device Utilization and Performance

    Contact Northwest Logic

    Getting Started

    Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

    IP Quality Metrics

    Basic
    Year IP was first released2005
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Expert technical support
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
    Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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