Expresso DMA Bridge Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Basic Functions: DMA

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Overview

The Northwest Logic Expresso DMA Bridge core provides high performance DMA and/or bridging between PCIe and AXI for both endpoint and rootport applications. Using the core eliminates the need for the user to implement their own DMA design significantly reducing development time and risk. In addition, Northwest Logic provides companion Windows and Linux Expresso DMA drivers. The Expresso DMA Driver works hand-in-hand with the Expresso DMA Bridge core. Contact Northwest Logic for more information. Northwest Logic also provides IP core customization services.

Features

    Device Utilization and Performance

    Contact Northwest Logic

    Getting Started

    Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

    IP Quality Metrics

    Basic
    Year IP was first released2014
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Expert technical support
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportWindows and Linux
    Implementation
    User InterfaceAXI; Other: Avalon-ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
    Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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