Integrated PCI Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Interface Protocols: PCI

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Overview

Northwest Logic's integrated PCI core is specifically designed to enable you to implement a high-performance PCI system with no additional PCI logic design. The integrated PCI core accomplishes this by integrating Northwest Logic's PCI core with a high-performance back-end module. The integrated PCI core enables the maximum possible PCI throughput to be achieved through the use of independent FIFO interfaces: master write, target write, master read, and target read. The FIFO interfaces support multiple posted writes, delayed reads, and read pre-fetching operations. In addition, the FIFO interfaces enable PCI bus and local bus data transfers to occur simultaneously. The core is available in several versions including 32 or 32/64 bit, target-only or master/target, and peripheral or host. The integrated PCI core is provided with Northwest Logic's PCI-X/PCI testbench. Contact Northwest Logic for more information.

Features

    Device Utilization and Performance

    Contact Northwest Logic

    Getting Started

    Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: \t Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

    IP Quality Metrics

    Basic
    Year IP was first released2004
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Expert technical support
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceOther: Contact Northwest Logic
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
    Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.