PCI Express (PCIe) Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Interface Protocols: PCI Express

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Expresso 3.0 Core is part of Northwest Logic's PCIe solution. This solution is designed to achieve maximum PCIe throughput while being easy to use. The Expresso 3.0 Core separately, or in combination with the Northwest Logic DMA Core and DMA Driver, provides the maximum system throughput on a PCIe link. The core is specifically designed for ease of use, including full release packet decoding, complete error handling, automatic handling of PCIe message packets, and comprehensive system debug and link monitoring support. The core is delivered integrated and verified with the target PHY and Expresso (PCIe) testbench. The core is fully compliant with the current version of the PCI Express Base Specification 3.0. The core includes all of the required 3.0 features including physical functions, SR-IOV, and flexible equalization support. To keep clock rates manageable, Northwest Logic also supplies a 256 bit side version of the core. Contact Northwest Logic for more information.

Features

    Device Utilization and Performance

    Contact Northwest Logic

    Getting Started

    Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

    IP Quality Metrics

    Basic
    Year IP was first released2005
    Latest version of Quartus supported17.0
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Any additional customer deliverables provided with IP
    Expert technical support
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedY
    Driver OS supportWindows and Linux
    Implementation
    User InterfaceAXI; Other: Avalon-ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
    Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?PCI SIG 3.0/2.1/1.1
    If yes, on which Altera device(s)?N/A
    If Yes, date performed
    11/19/2008
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.